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E2G0149-29-41
Semiconductor MSM514102D/DL
Semiconductor
This version: Apr. 1999 MSM514102D/DL
4,194,304-Word 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE
DESCRIPTION
The MSM514102D/DL is a 4,194,304-word 1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514102D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514102D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514102DL (the low-power version) is specially designed for lower-power applications.
FEATURES
* 4,194,304-word 1-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) * Static Column mode, read modify write capability * CS before RAS refresh, hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514102D/DL-xxSJ) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514102D/DL-xxZS) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM514102D/DL-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM514102D/DL-60 MSM514102D/DL-70 MSM514102D/DL-80 Access Time (Max.) tRAC 60 ns 70 ns 80 ns tAA 30 ns 35 ns 40 ns tCAC 15 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 110 ns 130 ns 150 ns 495 mW 440 mW 385 mW 5.5 mW/ 1.1 mW (L-version)
1/17
Semiconductor
MSM514102D/DL
PIN CONFIGURATION (TOP VIEW)
DIN 1 26 VSS 24 CS 22 A9 18 A8 17 A7 16 A6 15 A5 14 A4 A9 1 WE 2 NC 4 25 DOUT 23 NC DOUT 3 DIN 5 NC 9 RAS 7 2 CS DIN 1 RAS 3 A10 5 A0 9 4 VSS 6 WE WE 2 NC 4 RAS 3 8 A10 A0 11 A2 13 A5 17 A7 19 10 NC 12 A1 14 A3 16 A4 18 A6 20 A8 A10 5 A0 9 A1 10 A2 11 A3 12 VCC 15 A1 10 A2 11 A3 12 VCC 13 VCC 13 26/20-Pin Plastic SOJ 20-Pin Plastic ZIP 26/20-Pin Plastic TSOP (K Type) Pin Name A0 - A10 RAS CS DIN DOUT WE VCC VSS NC Function Address Input Row Address Strobe Chip Select Input Data Input Data Output Write Enable Power Supply (5 V) Ground (0 V) No Connection
26 VSS 24 CS 23 NC 22 A9 18 A8 17 A7 16 A6 15 A5 14 A4
25 DOUT
2/17
Semiconductor
MSM514102D/DL
BLOCK DIAGRAM
RAS CS
Timing Generator
Timing Generator
11
Column Address Buffers
11
Column Decoders
Write Clock Generator
WE
A0 - A10
Internal Address Counter
Refresh Control Clock
Sense Amplifiers
I/O Selector
Output Buffer
DOUT
11
Row Address Buffers
11
Row Decoders
Word Drivers
Memory Cells
Input Buffer
DIN
VCC
On Chip VBB Generator
VSS
3/17
Semiconductor
MSM514102D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A10, DIN) Input Capacitance (RAS, CS, WE) Output Capacitance (DOUT) Symbol CIN1 CIN2 COUT Typ. -- -- --
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 6 7 7 Unit pF pF pF
4/17
Semiconductor DC Characteristics
MSM514102D/DL
(VCC = 5 V 10%, Ta = 0C to 70C)
Symbol
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Condition
MSM514102 MSM514102 MSM514102 D/DL-60 D/DL-70 D/DL-80 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 V V mA 2.4 0 -10
VOH IOH = -5.0 mA VOL IOL = 4.2 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V DOUT disable 0 V VO 5.5 V RAS, CS cycling, tRC = Min. RAS, CS = VIH ICC2 RAS, CS VCC -0.2 V RAS cycling, ICC3 CS = VIH, tRC = Min. RAS = VIH, ICC5 CS = VIL, DOUT = enable ICC6 RAS cycling, CS before RAS RAS = VIL, ICC9 Address cycling, tSC = Min. tRC = 125 ms, ICC10 CS before RAS, tRAS 1 ms
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CS before RAS Refresh) Average Power Supply Current (Static Column Mode) Average Power Supply Current (Battery Backup)
ILO
-10
10
-10
10
-10
10
mA
ICC1
-- -- -- -- --
90 2 1 200 90
-- -- -- -- --
80 2 1 200 80
-- -- -- -- --
70 2 1 200 70
mA 1, 2
mA mA
1 1, 5
mA 1, 2
--
5
--
5
--
5
mA
1
--
90
--
80
--
70
mA 1, 2
--
80
--
70
--
60
mA 1, 3
--
300
--
300
--
300
mA
1, 4, 5
Notes : 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CS = VIH. VCC - 0.2 V VIH 6.5 V, -1.0 V VIL 0.2 V. L-version.
5/17
Semiconductor AC Characteristics (1/2)
MSM514102D/DL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Static Column Mode Cycle Time Static Column Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CS Access Time from Column Address Access Time from Last Write Output Enable Time referenced to WE Output Low Impedance Time from CS Data Output Hold Time referenced to Column Address Data Output Hold Time from WE CS to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Static Column Mode) RAS Hold Time CS Precharge Time (Static Column Mode) CS Pulse Width CS Hold Time CS to RAS Precharge Time RAS to CS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS (Write Cycle) Column Address Hold Time from RAS Column Address to RAS Lead Time Column Address Hold Time from RAS Precharge MSM514102 MSM514102 MSM514102 D/DL-70 D/DL-60 D/DL-80 Symbol Unit Note Min. tRC tRWC tSC tSRWC tRAC tCAC tAA tALW tOW tCLZ tAOH tWOH tOFF tT tREF tREF tRP tRAS tRASC tRSH tCP tCS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAWR tAR tRAL tAH 110 130 35 60 -- -- -- -- -- 0 5 0 0 3 -- -- 40 60 60 15 10 15 60 5 20 15 0 10 0 15 50 75 30 10 Max. -- -- -- -- 60 15 30 55 15 -- -- -- 15 50 16 128 -- 10,000
100,000
Min. 130 155 40 70 -- -- -- -- -- 0 5 0 0 3 -- -- 50 70 70 20 10 20 70 5 20 15 0 10 0 15 55 85 35 10
Max. -- -- -- -- 70 20 35 65 20 -- -- -- 20 50 16 128 -- 10,000
100,000
Min. 150 175 45 80 -- -- -- -- -- 0 5 0 0 3 -- -- 60 80 80 20 10 20 80 5 20 15 0 10 0 15 60 95 40 10
Max. -- -- -- -- 80 20 40 75 20 -- -- -- 20 50 16 128 -- 10,000
100,000
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 8 3 4, 5, 6 4, 5 4, 6, 7 4, 7 4 4
-- -- 10,000 -- -- 45 30 -- -- -- -- -- -- -- --
-- -- 10,000 -- -- 50 35 -- -- -- -- -- -- -- --
-- -- 10,000 -- -- 60 40 -- -- -- -- -- -- -- --
6/17
Semiconductor AC Characteristics (2/2)
MSM514102D/DL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Column Address Hold Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Invalid Time Write Command Hold Time (DOUT Disable) Write Command to RAS Lead Time Write Command to CS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS CS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time RAS to CS Set-up Time (CS before RAS) RAS to CS Hold Time (CS before RAS) WE Hold Time from RAS (CS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode)
Symbol
MSM514102 MSM514102 MSM514102 D/DL-60 D/DL-80 D/DL-70 Unit Note Min. Max. -- 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 65 20 0 0 0 0 10 50 10 10 0 20 20 0 15 55 20 35 70 10 5 10 10 10 10 10 Max. -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 75 20 0 0 0 0 15 60 15 10 0 20 20 0 15 60 20 40 80 10 5 10 10 10 10 10 Max. -- 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 11 11 10 9 9 10 7 55 20 0 0 0 0 10 45 10 10 0 15 15 0 15 50 15 30 60 10 5 10 10 10 10 10
tAHLW tRCS tRCH tRRH tWCS tWCH tWCR tWP tWI tWH tRWL tCWL tDS tDH tDHR tCWD tAWD tRWD tCSR tCHR tWRH tWTS tWTH
Last Write to Column Address Delay Time tLWAD
CS Active Delay Time from RAS Precharge tRPC
WE to RAS Precharge Time (CS before RAS) tWRP
7/17
Semiconductor Notes:
MSM514102D/DL
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. Operating within the tLWAD (Max.) limit ensures that tALW (Max.) can be met. tLWAD (Max.) is specified as a reference point only. If tLWAD is greater than the specified tLWAD (Max.) limit, then the access time is controlled by tAA. 8. tOFF (Max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.) and tAWD tAWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CS leading edge in an early write cycle, and to the WE leading edge in a read modify write cycle. 12. The test mode is initiated by performing a WE and CS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. RA10, CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, the data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/17
E2G0150-18-41U Semiconductor
TIMING WAVEFORM
Read Cycle
Address
Write Cycle (Early Write)
Address
, ,,
MSM514102D/DL
tRC tRP RAS VIH - VIL - tRAS tCRP tCSH tRCD tRSH tCRP CS VIH - VIL - VIH - VIL - tRAD tCS tASR tRAH tRAL tAH Row Column tAR tRCS tRRH tRCH WE VIH - VIL - tAA tCAC tRAC tOFF DOUT VOH - VOL - Open Valid Data tCLZ "H" or "L"
tRC
RAS
VIH - VIL -
tRAS
tRP
tAWR
tCRP
tCSH
CS
VIH - VIL -
tRSH tCS
tCRP
tRCD
tASR
tRAH
VIH - VIL -
Row
Column
tRAD
tASC
tCAH tWCR
WE
VIH - VIL -
tWCS
tWP
tWH
tDS
tDH
DIN
VIH - VIL - VOH - VOL -
Valid Data
tDHR
DOUT
Open
"H" or "L"
9/17
Semiconductor
Read Modify Write Cycle
Address
Static Column Mode Read Cycle
VIH - VIL - VIH - VIL - VIH - VIL -
Address
,, , ,
MSM514102D/DL
tRWC tRP RAS VIH - VIL - tRAS tCRP tRCD tRAD tRAL tCS tCRP CS VIH - VIL - tRCS tCWD tAWD tASR tRAH tCWL tRWL VIH - VIL - tCAH Row Column tRWD WE VIH - VIL - VIH - VIL - VOH - VOL - tWP tCSH tDS tDH DIN Valid Data tRAC tAA tCAC tWOH tOFF DOUT Open Valid Data tCLZ "H" or "L"
tRP RAS tRASC tCP CS tCS tRSH tCS tCRP tRCD tASR tRAH tSC tSC tRAL tAH Row Column Column Column tRAD tRCS tAR tCSH tRCH tRCS tRRH tRCH WE VIH - VIL - tCAC tAA tAA tOFF tAA tRAC tAOH tOFF tCAC DOUT VOH - VOL - tCLZ
Valid Data Valid Data
tCLZ
Valid Data
"H" or "L"
10/17
Semiconductor Static Column Mode Write Cycle (Early Write)
MSM514102D/DL
Static Column Mode Read Modify Write Cycle
,,,
tRP RAS VIH - VIL - VIH - VIL - VIH - VIL - tRASC tRAD tASC tCP tRSH tCRP CS tRCD tASR tRAH tRAL tCAH Address Row Column tAWR tASC tWCH tWCS Column tCAH Column tASC tCAH WE VIH - VIL - tCWL tWH tWP tSC tWCS tWI tDS tDS tDH tDH tDS tDH DIN VIH - VIL - VOH - VOL - Valid Data Valid Data
Valid Data
tDHR
DOUT
Open
"H" or "L"
tRASC
tRP
RAS CS
VIH - VIL -
tCWD
tCRP
VIH - VIL -
tRCS
tAWD
tLWAD
tCWL
tASR
tRAH
tRAL
tCAH
tRWL
Address
VIH - VIL -
Row
Column
Column
tRAD tRWD
tSRWC
tAWD
WE
VIH - VIL -
tWP
tRCD
tDS
tDH
DIN
VIH - VIL -
Valid Data
Valid Data
tRAC
tAA
tCAC
tWOH
tAA
tALW
tOW
tOFF
DOUT
VOH - VOL -
tCLZ
Valid Data
Valid Data "H" or "L"
11/17
Semiconductor
Static Column Mode Read/Write Mixed Cycle
RAS VIH - VIL - tRCD VIH - VIL - VIH - VIL -
Address
RAS-Only Refresh Cycle
Address
, , , ,,,
MSM514102D/DL
tASC tCP CS tRAD tCS tASR tRAH Row Column tAWR Column tSC Column tCAH WE VIH - VIL - tWCR tWCS tAWD tWP tDH tLWAD tDS tDH tDS DIN VIH - VIL - Valid Data tDHR Invalid Data tCAC tAA
Valid Data
tAOH
tAA
tWOH
DOUT
VOH - VOL -
tALW
Valid Data
Valid Data
(Read)
(Read/Write)
"H" or "L"
tRC
tRAS
tRP
RAS
VIH - VIL -
tRPC
tCRP
CS
VIH - VIL -
tASR
tRAH
VIH - VIL -
Row
tOFF
DOUT
VOH - VOL -
Open
Note: WE = "H" or "L"
"H" or "L"
12/17
Semiconductor
, ,, ,,,
CS before RAS Refresh Cycle
tRC tRP RAS VIH - VIL - tRAS tRPC tRPC tCSR tCP tCSR tCHR CS VIH - VIL - tWRP tWRH tWRP WE VIH - VIL - tOFF DOUT VOH - VOL - Open Note : Address = "H" or "L" "H" or "L"
MSM514102D/DL
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRP
tRAS
RAS
VIH - VIL -
tCRP
tRCD
tRSH
tCHR
tCRP
CS
VIH - VIL -
tAR
tRAH
tASR
tRAD
tRAL
tAH
Address
VIH - VIL -
Row
Column
tRCS
tRRH tWRP
tWRH
WE
VIH - VIL - VOH - VOL -
tCAC
tRAC
tAA
tOFF
DOUT
Valid Data
tCLZ
"H" or "L"
13/17
,,, , ,
Semiconductor MSM514102D/DL Hidden Refresh Write Cycle
tRC tRC tRAS tRP tRP
RAS
VIH - VIL -
tAR
tRAS
tCRP
tRCD
tRSH
tCHR
tCRP
CS
VIH - VIL -
tRAH
tASR
tRAD
tASC
tCAH
Address
VIH - VIL -
Row
Column
tWCS
tWH
tWRP
tWRH
WE
VIH - VIL - VIH - VIL - VOH - VOL -
tDS
tDH
DIN
Valid Data
tDHR
DOUT
Open
"H" or "L"
Test Mode Initiate Cycle
tRC
tRP
tRAS
RAS
VIH - VIL -
tRPC
tCP
tCSR
tCHR
CS
VIH - VIL -
tWTS
tWTH
WE
VIH - VIL -
tOFF
DOUT
VOH - VOL -
Open
Note: Address, DIN = "H" or "L"
"H" or "L"
14/17
Semiconductor
MSM514102D/DL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
15/17
Semiconductor
MSM514102D/DL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
16/17
Semiconductor
MSM514102D/DL
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
17/17
E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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